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3946
Half-Bridge Power MOSFET Controller
A3946KLB SOIC
Data Sheet 29319.150
VREG CP2 CP1 PGND GL S
1 2 3 4 5 6 7 8
16 VBB 15 VREF 14 DT 13 LGND 12 RESET 11 IN2
The A3946 is designed specifically for applications that require high power unidirectional dc motors, three-phase brushless dc motors, or other inductive loads. The A3946 provides two high-current gate drive outputs that are capable of driving a wide range of power N-channel MOSFETs. The high-side gate driver switches an N-channel MOSFET that controls current to the load, while the low-side gate driver switches an N-channel MOSFET as a synchronous rectifier. A bootstrap capacitor provides the above-battery supply voltage required for N-channel MOSFETs. An internal charge pump for the high side allows for dc (100% duty cycle) operation of the half-bridge. The A3946 is available in a choice of two power packages: a 16-lead SOIC with copper batwing power tab (part number suffix LB), and a 16-lead TSSOP with exposed thermal pad (suffix LP).
Scale 1:1
GH BOOT
10 IN1 9 ~FAULT
A3946KLP TSSOP with Exposed Thermal Pad
VREG CP2 CP1 PGND GL S GH 1 2 3 4 5 6 7 8 16 VBB 15 VREF 14 DT 13 LGND 12 RESET 11 IN2 10 IN1 9 ~FAULT
Scale 1:1
BOOT
FEATURES
On-chip charge pump for 7 V minimum input supply voltage High-current gate drive for driving a wide range of N-channel MOSFETs Bootstrapped gate drive with charge pump for 100% duty cycle Overtemperature protection Undervoltage protection -40C to 135C ambient operation
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB ............................. 60 V Logic Inputs ..................................-0.3 V to 6.5 V Pin S....... .........................................-4 V to 60 V Pin GH ...........................................-4 V to 75 V Pin BOOT..... ................................-0.6 V to 75 V Pin DT ........................................................ VREF Pin VREG ......................................-0.6 V to 15 V Package Thermal Resistance, RJA A3946KLB..................................... 48C/W1 A3946KLB..................................... 38C/W2 A3946KLP ..................................... 44C/W1 A3946KLP ..................................... 34C/W2 Operating Temperature Range, TA .. -40C to +135C Junction Temperature, TJ...........................+150C Storage Temperature Range, TS ....-55C to +150C
Always order by complete part number:
Part Number A3946KLB A3946KLP Package 16-Lead SOIC; Copper Batwing Power Tab 16-Lead TSSOP; Exposed Thermal Pad
Notes: 1. Measured on a two-sided PCB with 3 in.2 of 2 oz. copper. 2. Measured on JEDEC standard High-K board.
Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
Functional Block Diagram
+VBAT C1 0.47 uF, X7R V rated to VBAT C2 0.47 uF, X7R V rated to VBAT P VBB CP2 CP1
VREF +5 Vref 0.1 uF X7R 10 V L
Charge Pump ILIM
VREG CREG P
10 k
L
P Charge Pump
BOOT
~FAULT Protection VREG Undervoltage Overtemperature UVLOBOOT L VREF DT Turn-On Delay High Side Driver GH RGATE P Bootstrap UVLO CBOOT
RDEAD L
IN1
Control Logic VREG L
S
IN2 Low Side Driver
GL
RGATE
PGND L RESET P L LGND L P
Control Logic Table
IN1 X 0 0 1 1 0 0 1 1 IN2 X 0 1 0 1 0 1 0 1 DT Pin X RDEAD - LGND RDEAD - LGND RDEAD - LGND RDEAD - LGND VREF VREF VREF VREF RESET 0 1 1 1 1 1 1 1 1 GH Z L L L H L L H H GL Z H L L L L H L H Sleep mode Low-side FET ON following dead time All OFF All OFF High-side FET ON following dead time All OFF Low-side FET ON High-side FET ON CAUTION: High-side and low-side FETs ON Function
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
ELECTRICAL CHARACTERISTICS at TA = -40 to +135C, VBB = 7 to 60 V (unless otherwise noted)
Characteristics Symbol Test Conditions
RESET = High, Outputs Low RESET = Low VBB > 7.75 V, Ireg = 0 mA to 15 mA VBB = 7 V to 7.75 V, Ireg = 0 mA to 15 mA CP1, CP2 IREF 4 mA, CREF = 0.1 F
Limits Min. Typ.
3
Max.
6 10 13.5 13.5
Units
mA A V V kHz V
VBB Quiescent Current
IVBB
- -
12.0 11.0
-
13
VREG Output Voltage Charge Pump Frequency VREF Output Voltage
VREG FCP VREF
-
62.5
-
4.5
-
5.5
-
60 40 4 6 2 3
Gate Output Drive
Turn On Time Turn Off Time Pullup On Resistance trise tfall RDSUP CLOAD = 3300 pF, 20% to 80% CLOAD = 3300 pF, 80% to 20% Tj = 25C Tj = 135C Tj = 25C Tj = 135C tpw < 10 s tpw < 10 s tpw < 10 s, Bootstrap Capacitor fully charged
Pulldown On Resistance Short Circuit Current - Source Short Circuit Current - Sink GH Output Voltage GL Output Voltage
RDSDOWN
- - - - - -
800 1000 VREG - 1.5 VREG - 0.2
100 80
ns ns mA mA V V
- - - - - - - -
500 7 150
- -
VGH VGL
- - - -
350 6
-
Rdead = 5 k Rdead = 100 k Logic input to unloaded GH, GL. DT = VREF
Timing
Dead Time (Delay from Turn Off to Turn On) Propagation Delay tDEAD tPD 200 5 ns s ns
-
-
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
ELECTRICAL CHARACTERISTICS at TA = -40 to +135C, VBB = 7 to 60 V (unless otherwise noted)
Limits Characteristics
Protection
VREG Undervoltage VREG Undervoltage BOOT Undervoltage BOOT Undervoltage Thermal Shutdown Temperature Thermal Shutdown Hysteresis VREGON VREGOFF VBSON VBSOFF TJTSD TJ VREG increasing VREG decreasing VBOOT increasing VBOOT decreasing Temperature increasing Recovery = TJTSD - TJ 8.6 7.8 8 7.25 9.1 8.3 8.75 8.0 170 15 9.6 8.8 9.5 8.75 V V V V C C
Symbol
Test Conditions
Min.
Typ.
Max.
Units
- - - - -
2.0 2.2
- -
100 40 1
Logic
Input Current IIN(1) IIN(0) IN1 VIN / IN2 VIN = 2.0 V IN1 VIN / IN2 VIN = 0.8 V RESET pin only Logic Input Voltage VIN(1) IN1 / IN2 logic high RESET logic high VIN(0) Logic Input Hysteresis Fault Output Logic low All digital inputs I = 1 mA, fault asserted V=5V 40 16 A A A V V V mV mV A
-
100
-
Vol Voh
- -
- - - - - - -
- -
0.8 300 400 1
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
Functional Description
VREG. A 13 V output from the on-chip charge pump, used to power the low-side gate drive circuit directly, provides the current to charge the bootstrap capacitors for the high-side gate drive. The VREG capacitor, CREG, must supply the instantaneous current to the gate of the low-side MOSFET. A 10 F, 25 V capacitor should be adequate. This capacitor can be either electrolytic or ceramic (X7R). Diagnostics and Protection. The fault output pin, ~FAULT, goes low (i.e., FAULT = 1) when the RESET line is high and any of the following conditions are present: * Undervoltage conditions on VREG (UVREG) or on the internal logic supply VREF (UVREF). These conditions set a latched fault. * A junction temperature > 170C (OVERTEMP). This condition sets a latched fault. * An undervoltage on the stored charge of the BOOT capacitor (UVBOOT). This condition does NOT set a latched fault. An overtemperature event signals a latched fault, but does not disable any output drivers, regulators, or logic inputs. The user must turn off the A3946 (e.g., force the RESET line low) to prevent damage. The power FETs are protected from inadequate gate drive voltage by undervoltage detectors. Either of the regulator undervoltage faults (UVREG or UVREF) disable both output drivers until both voltages have been restored. The high-side driver is also disabled during a UVBOOT fault condition. Under many operating conditions, both the high-side (GH) and low-side (GL) drivers may be off, allowing the BOOT capacitor to discharge (or never become charged) and create a UVBOOT fault condition, which in turn inhibits the highside driver and creates a FAULT = 1. This fault is NOT latched. To remove this fault, momentarily turn on GL to charge the BOOT capacitor. Latched faults may be cleared by a low pulse, 1 to 10 s wide, on the RESET line. Throughout that pulse (despite a possible UVBOOT), FAULT = 0; also the fault latch is cleared immediately, and remains cleared. If the power is restored (no UVREG or UVREF), and if no OVERTEMP fault exists, then the latched fault remains cleared when the RESET line returns to high. However, FAULT = 1 may still occur because a UVBOOT fault condition may still exist. Charge Pump. The A3946 is designed to accommodate a wide range of power supply voltages. The charge pump output, VREG, is regulated to 13 V nominal. In all modes, this regulator is current-limited. When VBB < 8 V, the charge pump operates as a voltage doubler. When 8 V < VBB< 15 V, the charge pump operates as a voltage doubler/PWM, current-controlled, voltage regulator. When VBB>15 V, the charge pump operates as a PWM, current-controlled, voltage regulator. Efficiency shifts, from 80% at VBB= 7 V, to 20% at VBB = 50 V. CAUTION. Although simple paralleling of VREG supplies from several A3946s may appear to work correctly, such a configuration is NOT recommended. There is no assurance that one of the regulators will not dominate, taking on all of the load and back-biasing the other regulators. (For example, this could occur if a particular regulator has an internal reference voltage that is higher that those of the other regulators, which would force it to regulate at the highest voltage.) Sleep Mode/Power Up. In Sleep Mode, all circuits are disabled in order to draw minimum current from VBB. When powering up and leaving Sleep Mode (the RESET line is high), the gate drive outputs stay disabled and a fault remains asserted until VREF and VREG pass their undervoltage thresholds. When powering up, before starting the first bootstrap charge cycle, wait until t = CREG 4 (where CREG is in F, and t is in ns) to allow the charge pump to stabilize. When powered-up (not in Sleep Mode), if the RESET line is low for > 10 s, the A3946 may start to enter Sleep Mode (VREF < 4 V). In that case, ~FAULT = 1 as long as the RESET line remains low. If the RESET line is open, the A3946 should go into Sleep Mode. However, to ensure that this occurs, the RESET line must be grounded.
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
Dead Time. The analog input pin DT sets the delay to turn on the high- or low-side gate outputs. When instructed to turn off, the gate outputs change after an short internal propagation delay (90 ns typical). The dead time controls the time between this turn-off and the turn-on of the appropriate gate. The duration, tDEAD, can be adjusted within the range 350 ns to 6000 ns using the following formula: tDEAD = 50 + (RDEAD 16.7 ) where tDEAD is in ns, and RDEAD is in , and should be in the range 5 k < RDEAD < 100 k. Do not ground the DT pin. If the DT pin is left open, dead time defaults to 12 s. Control Logic. Two different methods of control are possible with the A3946. When a resistor is connected from DT to ground, a single-pin PWM scheme is utilized by shorting IN1 with IN2. If a very slow turn-on is required (greater than 6 s), the two input pins can be hooked-up individually to allow the dead times to be as long as needed.
The dead time circuit can be disabled by tying the DT pin to VREF. This disables the turn-on delay and allows direct control of each MOSFET gate via two control lines. This is shown in the Control Logic table, on page 2. Top-Off Charge Pump. An internal charge pump allows 100% duty cycle operation of the high-side MOSFET. This is a low-current trickle charge pump, and is only operated after a high-side has been signaled to turn on. A small amount of bias current (< 200 A) is drawn from the BOOT pin to operate the floating high-side circuit. The charge pump simply provides enough drive to ensure that the gate voltage does not droop due to this bias supply current. The charge required for initial turn-on of the high-side gate must be supplied by bootstrap capacitor charge cycles. This is described in the section Application Information. VREF. VREF is used for the internal logic circuitry and is not intended as an external power supply. However, the VREF pin can source up to 4 mA of current. A 0.1 F capacitor is needed for decoupling.
Fault Response Table Fault Mode No Fault BOOT Capacitor Undervoltage VREG Undervoltage VREF Undervoltage Thermal Shutdown Sleep
1
RESET 1
2
~FAULT 1 0 0 0 0 1
VREG ON ON ON OFF ON OFF
VREF ON ON ON ON ON OFF
GH1 (IL) 0 0 0 (IL) High Z
GL1 (IL) (IL) 0 0 (IL) High Z
1 1 1 1 0
3
4
3
5
(IL) indicates that the state is determined by the input logic. 2 This fault occurs whenever there is an undervoltage on the BOOT capacitor. This fault is not latched. 3 These faults are latched. Clear by pulsing RESET = 0. 4 Unspecified VREF undervoltage threshold < 4 V. 5 During power supply undervoltage conditions, GH and GL are instructed to be 0 (low). However, with VREG < 4 V, the outputs start to become high impedance (High Z). Refer to the section Sleep Mode/Power Up.
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
Application Information
Bootstrap Capacitor Selection. CBOOT must be correctly selected to ensure proper operation of the device. If too large, time is wasted charging the capacitor, with the result being a limit on the maximum duty cycle and PWM frequency. If the capacitor is too small, the voltage drop can be too large at the time the charge is transferred from the CBOOT to the MOSFET gate. To keep the voltage drop small:
QBOOT >> QGATE
At power-up and when the drivers have been disabled for a long time, the bootstrap capacitor can be completely discharged. In this case, Delta_v can be considered to be the full high-side drive voltage, 12 V. Otherwise, Delta_v is the amount of voltage dropped during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the S pin is pulled low, via a GL PWM cycle, and current flows from VREG through the internal bootstrap diode circuit to CBOOT. Power Dissipation. For high ambient temperature applications, there may be little margin for on-chip power consumption. Careful attention should be paid to ensure that the operating conditions allow the A3946 to remain in a safe range of junction temperature. The power consumed by the A3946 can be estimated as:
P_total = Pd_bias + Pd_cpump + Pd_switching_loss
where a factor in the range of 10 to 20 is reasonable. Using 20 as the factor: and
QBOOT = CBOOT x VBOOT = QGATE x 20 CBOOT = QGATE x 20 / VBOOT
The voltage drop on the BOOT pin, as the MOSFET is being turned on, can be approximated by:
Delta_v = QGATE / CBOOT
where:
Pd_bias = VBB x IVBB , typically 3 mA,
For example, given a gate charge, QGATE, of 160 nC, and the typical BOOT pin voltage of 12 V, the value of the Boot capacitor, CBOOT, can be determined by:
CBOOT = (160 nC x 20) / 12 V 0.266 F
and
Pd_cpump = (2VBB - VREG) IAVE, for VBB < 15 V, or Pd_cpump = (VBB - VREG) IAVE, for VBB > 15 V,
Therefore, a 0.22 F ceramic (X7R) capacitor can be chosen for the Boot capacitor. In that case, the voltage drop on the BOOT pin, when the high-side MOSFET is turned on, is:
Delta_v = 160 nC / 0.22 F = 0.73 V
in either case, where and
IAVE = QGATE x 2 x fPWM
Pd_switching_loss = QGATE
x VREG x 2 x fPWM Ratio,
Bootstrap Charging. It is good practice to ensure that the high-side bootstrap capacitor is completely charged before a high-side PWM cycle is requested. The time required to charge the capacitor can be approximated by:
tCHARGE = CBOOT (Delta_v / 100 mA)
where
Ratio = 10 / (RGATE + 10 ).
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
Application Block Diagrams
+VBAT
C2 10 F P CP2
C1 0.47 F
CP1
VREF
VREF +5 Vref 0.1 uF L L P
Charge Pump ILIM
VREG
10 k
P Charge Pump BOOT
CREG 10 F
~FAULT Protection VREG Undervoltage Overtemperature UVLOBOOT L High Side Driver GH RGATE 33 200 k IN1 Control Logic VREG L IN Brake IN2 Low Side Driver PGND External +5 V L RESET P L LGND L P M DC Motor GL RGATE 33 S P Bootstrap UVLO CBOOT 0.47 F IRF2807
DT
Turn-On Delay
RDEAD 15.8 k L IN Forward
IRF2807
Diagram A. Dependent drivers. Unidirectional motor control with braking and dead time. TDEAD = 1 s; QTOTAL = 160 nC.
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
+VBAT
C2 10 F P CP2
C1 0.47 F
CP1
VREF
VREF +5 Vref 0.1 uF L L P
Charge Pump ILIM Charge Pump
VREG P
10 k
CREG P 10 F BOOT M
~FAULT Protection VREG Undervoltage Overtemperature UVLOBOOT L High Side Driver GH RGATE 33 200 k IN1 Control Logic S Bootstrap UVLO CBOOT 0.47 F IRF2807 DC Motor #2
VREF
DT
Turn-On Delay
DC Motor #1 Forward Slow Decay DC Motor #2 Forward Slow Decay External +5 V L RESET P L L IN2 GL Low Side Driver PGND LGND L
VREG IRF2807 RGATE 33 M DC Motor #1
200 k
P
Diagram B. Independent drivers. One high-side drive and one low-side drive.
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
+VBAT
C2 10 F P CP2
C1 0.47 F P CP1
VREF
VREF +5 Vref 0.1 uF L L P
Charge Pump ILIM
VREG
10 k
P Charge Pump BOOT
CREG 10 F M DC Motor #1 M DC Motor #2
~FAULT Protection VREG Undervoltage Overtemperature UVLOBOOT L High Side Driver GH RGATE 33 200 k IN1 Control Logic VREG DC Motor #2 Forward Slow Decay External +5 V L RESET L IN2 Low Side Driver PGND P L LGND L P GL RGATE 33 200 k S P IRF2807 Bootstrap UVLO
IRF2807
VREF
DT
Turn-On Delay
DC Motor #1 Forward Slow Decay
Diagram C. Independent drivers. Two low-side drives.
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
+VBAT
P
C2 10 F
C1 0.47 F
CP2
CP1
VREF
VREF +5 Vref 0.1 uF L L P
Charge Pump ILIM Charge Pump
VREG
10 k
P BOOT
CREG 10 F
~FAULT Protection VREG Undervoltage Overtemperature UVLOBOOT L High Side Driver GH RGATE 33 200 k Forward IN1 Control Logic VREG Reverse IN2 CAUTION: ShootThrough Possible L RESET P L LGND L P Low Side Driver PGND External +5 V M DC Motor L GL RGATE 33 IRF2807 S P Bootstrap UVLO CBOOT 0.47 F IRF2807
VREF
DT
Turn-On Delay
Diagram D. Dependent drivers with independent controls. Unidirectional, motor control with brake/coast, but without dead time control.
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
Pin Name
VREG CP2 CP1 PGND* Gate drive supply.
Pin Description
SOIC-16 (A3946KLB)
1 2 3 4
TSSOP-16 (A3946KLP)
1 2 3 4
Charge pump capacitor, positive side. When not using the charge pump, leave this pin open. Charge pump capacitor, negative side. When not using the charge pump, leave this pin open. External ground. Internally connected to the power ground. Low-side gate drive output for external MOSFET driver. External series gate resistor can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output. Directly connected to the load terminal. The pin is also connected to the negative side of the bootstrap capacitor and negative supply connection for the floating high-side drive. High-side gate drive output for N-channel MOSFET driver. External series gate resistor can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output. High-side connection for bootstrap capacitor, positive supply for the high-side gate drive. Diagnostic output, open drain. Low during a fault condition. Logic control. Logic control. Logic control input. When RESET = 0, the chip is in a very low power sleep mode. External ground. Internally connected to the logic ground. Dead Time. Connecting a resistor to GND sets the turn-on delay to prevent shoot-through. Forcing this input high disables the dead time circuit and changes the logic truth table. 5 V internal reference decoupling terminal. Supply Input.
GL
5
5
S
6
6
GH
7
7
BOOT ~FAULT IN1 IN2 RESET LGND* DT VREF VBB
8 9 10 11 12 13 14 15 16
8 9 10 11 12 13 14 15 16
*In the LB package, the PGND pin (4) and LGND pin (13) grounds are internally connected by the leadframe. In the LP package, however, the PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally. In the LP package, the exposed thermal pad is not connected to any pin, but should be externally connected to ground, to reduce noise pickup by the pad.
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
A3946KLB SOIC
.406 10.31 .398 10.11 16 8 0 .011 0.28 .009 0.23
.299 7.59 .291 7.39 .414 10.52 .398 10.11 .040 1.02 .020 0.51
1
2
.020 0.51 .014 0.36 .026 0.66 REF
.050 1.27 BSC
.104 2.64 .096 2.44 .012 0.30 .004 0.10
Dimensions in inches Metric dimensions (mm) in brackets, for reference only
Webbed lead frame. Leads 4 and 13 are joined together within the device package.
A3946KLP TSSOP with Exposed Thermal Pad
5.1 4.9 16 0.201 0.193 8 0 0.20 0.008 0.09 0.004
4.5 0.177 4.3 0.169 6.6 0.260 6.2 0.244
A
3 0.118 BSC 1 0.039 REF
1
2
3 0.118 BSC
.75 .45
0.030 0.018
.25 0.010 BSC Seating Plane Gauge Plane
.30 .19
0.012 0.007
.65 .026 BSC
1.20 0.047 MAX .15 0.006 .00 0.000
Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only A Exposed thermal pad (bottom surface)
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Supplied in standard sticks/tubes of 49 devices or add "TR" to part number for tape and reel.
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Data Sheet 29319.150
3946 Half-Bridge Power MOSFET Controller
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright(c)2003, 2004 AllegroMicrosystems, Inc.
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